1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, relates to a nonvolatile semiconductor memory device that can store multi-level data having three or more levels in a nonvolatile manner. More specifically, the present invention relates to a configuration for implementing a multi-level nonvolatile semiconductor memory device that stores multi-level data by utilizing an internal configuration of a nonvolatile semiconductor memory device for storing binary data.
2. Description of the Background Art
In a nonvolatile semiconductor memory device for storing data in a nonvolatile manner, a memory cell is formed of a single transistor. Such a memory cell transistor has a floating gate that is formed between a control gate and a substrate region. This floating gate is electrically isolated from its surrounding and the threshold voltage of the memory cell transistor is determined depending on the amount of charges (electrons) accumulated in the floating gate. In a memory cell (Single Level Cell: SLC) for storing binary data of “1” and “0,” the states of a high threshold voltage and a low threshold voltage are correlated with each data value of the binary data. Generally, the state of a low threshold voltage is referred to as an erased state and is correlated with data “1”, while the state of a high threshold voltage is referred to as a programmed state (written state) and is correlated with the state where data “0” is stored.
A nonvolatile memory cell is formed of one transistor and therefore, has an advantages that the area occupied by the cell is small and data can be stored in a nonvolatile manner.
In order to store a large amount of data such as audio data and video data, it is required to increase the storage capacity. In order to satisfy such requirement, the specification of a multi-level memory cell (MLC: Multi-Level Cell) for storing data of two or more bits in one memory cell has been implemented. Multi-level data (data formed of two or more bits) instead of binary data is stored in a memory cell and therefore, the storage capacity can be increased while suppressing an increase in the area of the memory device. Such a nonvolatile semiconductor memory device for storing multi-level data is disclosed in, for example, Prior Art Document 1 (Japanese Patent Laying-Open No. 2001-6375), Prior Art Document 2 (Japanese Patent Laying-Open No. 11-25682) and others.
Document 1 discloses a configuration for storing multi-level data by compressing data supplied via the same data terminal at different timings, to produce compressed data for writing into a memory cell.
In the configuration disclosed in Document 2, predetermined operational processing is applied to 2 bit data at the time when storage data is produced, so that the data is converted to 4-level data that correspond to threshold voltage levels. Data writing is performed by extracting charges (electrons) from the floating gate in accordance with bit “1” that is included in this 4-level data. The storage data of a latch circuit that is arranged corresponding to a corresponding sense amplifier is set at bit “0” when writing is completed. Writing is competed when the entire data of the latch circuits are set to the writing completed state. Read out of data is performed by changing the voltage of a word line in multiple stages in data reading out.
Furthermore, Prior Art Document 3 (Japanese Patent Laying-Open No. 10-92186) discloses a configuration in which each of the threshold voltages is correlated with gray code data sequentially starting from the lowest threshold voltage when multi-level data is stored. Data detection in binary searching method in data read out is made easy by correlating the gray-coded data to the threshold voltages. A latch circuit is provided corresponding to each of the bit lines, so that latch data in the latch circuit is verified in accordance with the latched data of the latch circuit and the read-out data for verification in data writing and then the latched data is set at the write-in completed state when the latched data and the read-out data coincide with each other so as to carry out the programming only on memory cells where programming is required.
Prior Art Document 4 (Japanese Patent Laying-Open No. 10-55688) discloses a NAND type flash memory provided with a page buffer in order to carry out data writing in page units. In this Document 4, data read out is performed by one value at a time by varying the word line voltage sequentially and after this read-out, an addition circuit is used to convert the multi-level data into multi-bit data for storage in the page buffer.
Prior Art Document 5 (Japanese Patent Laying-Open No. 7-37393) discloses a serial sense circuit that reads out data serially from one memory cell by using a sense amplifier in read-out of multi-level data. In this serial sense circuit, a reference voltage and a memory cell read-out potential are compared, and the next comparison reference voltage is selected in accordance with the result of the comparison and is again compared with the memory cell read-out voltage. Thus, storage data, or 2-bit data in the case of 4-level data, in a single memory cell are sequentially read-out.
Prior Art Document 6 (Japanese Patent Laying-Open No. 6-309890) discloses a nonvolatile semiconductor memory device that switches the storage between 4-level data and 2-level (binary) data in accordance with a control signal. In the configuration shown in the Document 6, a sense circuit is provided exclusively to each mode for 2-level data and 4-level data and the write voltage levels for bit lines are switched between 2-value mode and 4-value mode in accordance with the control signal instructing 4 levels or 2 levels in the program circuit. Document 6 shows a configuration for accessing one memory cell.
It is desirable to implement an SLC configuration and an MLC configuration in the same chip from the view points of product management and design efficiency. However, in Documents 1 and 2, only the configuration of a multi-level memory is taken into account while the structure for coexisting an SLC configuration and an MLC configuration is not taken into consideration.
In addition, data conversion is performed such that bits in the same positions of different data are written in one memory cell in Documents 1, 2 and 6. In such a case, one memory cell stores data bits of different addresses to make the allocations of addresses complicated and therefore, it becomes difficult to coexist an SLC configuration and an MLC configuration that are different in number of address bits
In the configuration shown in Document 3, the data stored in a memory cell is converted into a gray code in accordance with threshold voltages. However, the configuration shown in this Document 3, relates to a circuit for carrying out data writing in page (word line) units by storing write data in latch circuit provided corresponding to each bit line, and the configuration for data writing in byte units is not taken into consideration. In addition, allocation of addresses for switching between an SLC configuration and an MLC configuration or coexistence of SLC configuration and MLC configuration is not taken into consideration.
In Document 4, a page buffer is utilized for converting two-bit data to four values to perform data writing one level (value) at a time, while one value is read out at a time by sequentially varying the word line voltage upon data read out so that two-bit data is generated based on the result of this read-out. In data read out the word line voltage is changed and a problem arises that a long period of time is required for data read-out. In addition, allocation of addresses is not taken into consideration in this Document 4, too.
In Document 5, a sense amplifier is used and the comparison basis potential serving as the comparison reference for the memory cell potential is changed to read out data in the same memory cell in a serial manner. However, the configuration for stably generating the basis voltage for the comparison is not taken into consideration. In addition, allocation of addresses for allowing the coexistence of an SLC configuration and an MLC configuration is not taken into consideration.
Document 6 shows a configuration for switching an SLC configuration and an MLC configuration by means of a control signal. However, input/output of data is performed in units of one bit or two bits in the configuration disclosed in this Document 6 and a configuration for writing in and for reading out data words in byte units is not taken into consideration. In addition, a sense amplifier for reading out 4-level data and a sense amplifier for reading out 2-level data are separately provided in the configuration shown in this Document 6 and therefore, the circuit configuration is redundant and a problem of increased circuit layout area arises. Moreover, efficient allocation of addresses for allowing the coexistence of SLC configuration and an MLC configuration is not taken into consideration.
Further, Documents 1 to 3 and 6 show a NAND type flash memory in which data writing is performed in page units and do not show a configuration of an NOR-type flash memory wherein data writing is performed by utilizing channel hot electrons. In addition, a configuration for implementing both the page mode operation and the random access operation in such a memory device is not taken into consideration.